Equivalent oxide thickness (EOT)

In plain words

A way of comparing : the thickness of plain silicon dioxide that would do the same job. A smaller number means the gate controls the more strongly.

Going deeper

Equivalent oxide thickness restates any gate insulator as the thickness of plain silicon dioxide that would give the same capacitance. A physically thicker layer of a stronger dielectric can grip the channel just as firmly while leaking far less – which is why the number, not the thickness, is what gets quoted.

One number for very different stacks

A gate controls a channel through its capacitance per unit area, which for a simple is κε₀ divided by the thickness. Two insulators with the same ratio of κ to thickness therefore give the same control, however different they are. EOT expresses that by rescaling to silicon dioxide: EOT = physical thickness × 3.9/κ. Five nanometres of a κ = 20 oxide has an EOT of about one nanometre.

The practical gain is leakage. Tunnelling through an insulator falls exponentially with physical thickness, so the thicker high-κ layer passes far less current for the same electrostatic control – the reason hafnium-based oxides replaced silicon dioxide in silicon technology in the late 2000s.

Why 2D channels make it hard

Growing a thin, uniform oxide on a is difficult precisely because its surface is inert. relies on reactive sites, and a pristine basal plane has none, so films nucleate in islands and leave pinholes until they are thick – which defeats the purpose. The workarounds all have costs: seeding with a metal that is then oxidised, functionalising the surface, depositing a buffer that adds to the EOT, or using a native oxide of another 2D crystal.

Crystalline insulators are an alternative: hBN is clean but has a modest κ of about 4, so it buys little; crystalline fluorides such as CaF₂ have been grown on 2D channels with the aim of combining a clean interface with a thin equivalent thickness.

Reading the number

EOT is a capacitance restated, so it depends on how the capacitance was measured – frequency, area, fringing fields and the correction for quantum capacitance in a thin channel all matter, and small devices are hard to measure at all. An EOT quoted without the leakage current density at a stated voltage is half a result, because the trade-off between the two is the whole point.

Interface quality matters as much as thickness. Traps at the interface store charge, cause and degrade the subthreshold slope, so a stack with a slightly larger EOT and a clean interface often makes a better transistor than a thinner one with a poor one.

For specialists

The SiO₂ thickness that would give the same gate capacitance as the actual dielectric stack.

Where this comes from

Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors Illarionov et al. · Nature Electronics 2, 230 (2019) cited by 326

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Metal, semimetal and insulator

The three basic ways a solid treats electricity, set by how its electrons fill the energies open to them. In a metal they fill a band of energies only partly, so the smallest push sets them moving, and it conducts at any temperature. In an insulator they fill a band completely and a wide gap separates it from the next, so nothing can move. A semimetal sits in between: two bands just touch or overlap a little, leaving a small number of mobile electrons and holes. NbSe₂ is a metal, graphene a semimetal, hBN an insulator.

A classification by where the Fermi level falls in the band structure. In a metal it crosses a partly filled band, leaving a Fermi surface, a carrier density of order one per atom (about 10²² cm⁻³) and a resistivity that falls on cooling. In a band insulator it lies in a gap of several electronvolts; a semiconductor is an insulator whose gap is small enough to be doped or gated. A semimetal has a slight overlap between conduction and valence bands (graphite, bismuth, bulk WTe₂) or bands that touch at isolated points (graphene), giving low and nearly equal densities of electrons and holes. Interactions can open gaps that band theory does not predict: Mott insulators from half-filled bands, excitonic insulators from semimetals.

Full explanation

Atomic layer deposition (ALD)

A way to coat a surface one layer of atoms at a time. Two chemicals take turns: the first sticks to every free spot on the surface but not to itself, the excess is pumped away, and the second reacts with what stuck, leaving one thin layer of, say, aluminium oxide. Repeating the pair builds the film with a precision of a fraction of a nanometre, even over deep, steep structures. It is how the gate insulators of modern computer chips are made – and on 2D materials it runs into a problem: their clean surfaces give the first chemical nothing to stick to.

Thin-film growth by alternating, self-limiting surface reactions of two precursors separated by purges – for Al₂O₃ trimethylaluminium and water, for HfO₂ a hafnium amide or chloride with water or ozone – typically at 100 to 300 °C, giving about 0.1 nm per cycle with sub-nanometre control and conformal coverage. It is the standard route to high-κ gate dielectrics in silicon CMOS. On the dangling-bond-free basal planes of graphene, TMDCs and hBN the first precursor finds no reactive sites, so nucleation starts only at steps, defects and residues, giving islands and pinholes. Seed layers (evaporated and oxidised Al, molecular layers), ozone or plasma functionalisation, low-temperature physisorption, or transferred and native-oxide dielectrics are used instead, each at a cost in thickness, interface traps or channel damage.

Full explanation