Field-effect transistor (FET)

Everyday term

In plain words

The electronic switch at the heart of every chip. It works like a tap: a voltage on one terminal, the gate, opens or closes a channel through which current flows. Researchers test new by making them into the channel of such a switch.

Going deeper

A 2D transistor and the curve used to judge it. The steep part of the transfer curve gives the subthreshold swing, which a conventional transistor cannot push below about 60 mV per tenfold change in current at room temperature; a gap between the forward and reverse sweeps is hysteresis from charge traps.

How the gate switches the channel

The gate, the and the channel form a capacitor. Above the the gate draws carriers into the channel – roughly the dielectric capacitance per area times the voltage beyond threshold – and current flows between source and drain; below it the channel empties and the current falls off exponentially.

How well the gate keeps control as a transistor shrinks depends on the channel thickness. In a thick channel, parts of it lie far from the gate and the drain starts to take over; these effects pushed silicon from planar transistors to fins and then to stacked wrapped by the gate. A 2D channel is under a nanometre thick all the way through, so the gate keeps hold of it at very short gate lengths. That, rather than , is the main reason 2D appear in industry plans for the most scaled transistors.

Reading a transfer curve

The standard measurement sweeps the at a fixed drain voltage and plots the drain current on a logarithmic axis. The compares the current at the two ends of the sweep, and means little without the voltage range it was taken over. The is the gate voltage needed to raise the current tenfold in the steep region; because carriers must be lifted thermally over a barrier, it cannot fall below about 60 mV per decade at room temperature in a conventional transistor. The threshold voltage marks where the channel turns on, and its spread across many devices says more about a process than the best single device does. Sweeping the gate back again reveals : if the two curves do not overlap, traps near the channel are filling and emptying.

Why published numbers are hard to compare

Many 2D transistors are gated from below through the silicon and roughly 300 nm of oxide, the thickness that makes flakes visible under a microscope. Such a gate couples weakly, so swings of hundreds of millivolts per decade describe the test structure rather than the material.

Contacts are the second trap. Metals deposited on 2D semiconductors form and often pin the , so can dominate, and a mobility taken from a two-terminal measurement then describes the contacts as much as the channel. or measurements separate the two. Mobility from transistor curves also depends on the gate capacitance assumed; with ionic liquids or thin high-k films a wrong capacitance can inflate it several times over.

For specialists

A three-terminal device in which a gate voltage modulates the of a semiconductor channel between source and drain through a thin dielectric. For 2D channels the key figures of merit are on/off ratio, subthreshold swing, mobility, contact resistance, hysteresis and threshold-voltage variability.

Where this comes from

MoS₂ transistors with 1-nanometer gate lengths Desai et al. · Science 354, 99 (2016) cited by 1,522

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Complementary metal–oxide–semiconductor (CMOS)

The way almost every digital chip is built. Each logic gate pairs a transistor that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A 2D material becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.

Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, threshold voltages held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for back-end-of-line integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe₂ is the leading p-type candidate.

Full explanation

Gating

Changing a material by putting a voltage on a nearby electrode – a gate – separated from it by an insulator. The voltage pulls electrons into the material or pushes them out, as in every transistor. Because a 2D material is so thin, the gate reaches all of it, so the number of electrons can be dialled up and down continuously: a single device can be turned from insulator to metal, its magnetism strengthened, or superconductivity switched on. Two gates, above and below, can also apply an electric field across the layer.

Electrostatic control of carrier density and electric field through a gate coupled capacitively across a dielectric: the induced density equals the gate capacitance times the voltage beyond threshold, divided by the electron charge, reaching a few 10¹³ cm⁻² with oxide or hBN gates before breakdown. Dual gating sets density and perpendicular displacement field independently, opening the gap of bilayer graphene and tuning moiré flat bands. Ionic-liquid and solid-electrolyte gating form an electric double layer about a nanometre thick and reach 10¹⁴–10¹⁵ cm⁻², enough to induce superconductivity in MoS₂ or raise the Curie temperature of Fe₃GeTe₂, but can intercalate or react electrochemically and work only while the ions are mobile. Hysteresis from traps, contact effects and quantum capacitance are the usual caveats.

Full explanation

On/off ratio

How much more current a transistor lets through when it is switched on than when it is switched off. A switch for digital logic needs at least ten thousand, and far more in chips that spend most of their time idle; graphene, which has no band gap, manages only about ten, which is why it cannot replace silicon in logic.

The ratio of the drain current with the transistor switched on to the current with it switched off, at a stated supply voltage. Below threshold the current falls at best tenfold per 60 mV of gate voltage at room temperature, so a ratio of 10⁶ needs at least 0.36 V of swing, and the off current is floored by leakage over the gap, band-to-band and source-to-drain tunnelling, and gate leakage. Monolayer MoS₂ transistors reached about 10⁸; gapless graphene stays near 10 at room temperature. Benchmarks compare the on current at a fixed off current and supply voltage rather than the ratio alone.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Resistivity and sheet resistance

Two ways to put a number on how strongly a material resists a current. Resistivity belongs to the material itself, whatever the size of the piece: copper’s is tiny, glass’s enormous. For a sheet so thin that its thickness is hard to pin down, the sheet resistance is used instead: the resistance of a square of it, measured from one edge to the opposite one, which comes out the same for a square of any size. It is quoted in ohms per square.

Resistivity ρ relates electric field to current density, in Ω·m or Ω·cm, so that a bar of length L and cross-section A has resistance ρL/A. For a film of thickness t the sheet resistance is ρ/t, quoted in Ω per square, and a strip L long and W wide has the sheet resistance times L/W. For an atomically thin layer it is the natural quantity, since the thickness is a convention, and it equals 1/neμ for sheet density n and mobility μ. Both are measured with four probes – a Hall bar, a collinear four-point probe or the van der Pauw method for arbitrary shapes – so that the voltage is sensed away from the current contacts and the contact resistance drops out.

Full explanation