Dielectric

Also called gate insulator

In plain words

An electrical used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a ’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high , so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

Going deeper

A dielectric blocks current but polarises in an electric field, so a capacitor stores more charge with it than without. In a transistor it separates the gate from the 2D channel, where it should be thin, high in permittivity and free of traps; leakage, trapped charge and breakdown are what make it fail.

Blocking current, passing the field

Put an insulator between the plates of a capacitor and it polarises: its electrons shift slightly against its nuclei, or its ions against each other, and the field inside is partly cancelled. More charge can then be stored at the same voltage, by a factor called the permittivity or dielectric constant, κ. In a transistor the dielectric is the layer between gate and channel, and the charge a pulls into the channel grows with κ and falls with the thickness.

Silicon technology thinned its silicon dioxide gate insulator until it was barely a nanometre thick and electrons began to tunnel straight through it. From 2007 hafnium-based oxides, with five to six times the permittivity, took over: physically thicker, so they leak less, yet electrically as effective as a much thinner layer of silicon dioxide.

What a 2D channel needs

A 2D channel is all surface, so whatever touches it matters. The ideal dielectric would be thin, high in κ, free of charged defects and bonded to the channel without disturbing it. hBN comes closest on the last points: placing graphene on hBN instead of silicon dioxide improved its almost tenfold, because hBN is flat, inert and nearly free of trapped charge. But its permittivity is low, and growth of hBN of high quality is still difficult.

The usual industrial route, of oxides, struggles because the basal planes of offer nothing to bond to. Researchers therefore try seed layers, crystalline fluorides such as CaF₂ that meet the channel through a clean interface, and oxides grown from the material itself, such as Bi₂SeO₅ formed on Bi₂O₂Se.

Judged by reliability

A dielectric that works in one measurement can still fail in a product. Charge trapped in the oxide or at its interface shifts the and causes ; under long stress at operating voltage and temperature, thresholds drift and the layer eventually breaks down. Industry judges dielectrics by statistics over many devices and by accelerated lifetime tests, and that is where many 2D gate stacks reported with excellent single devices are still weakest.

For specialists

An insulator characterised by its permittivity κ, and to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Where this comes from

High dielectric constant oxides Robertson · European Physical Journal Applied Physics 28, 265 (2004)
Boron nitride substrates for high-quality graphene electronics Dean et al. · Nature Nanotechnology 5, 722 (2010) cited by 7,165
Insulators for 2D nanoelectronics: the gap to bridge Illarionov et al. · Nature Communications 11, 3385 (2020) cited by 559
A native oxide high-κ gate dielectric for two-dimensional electronics Li et al. · Nature Electronics 3, 473 (2020) cited by 306

Metal, semimetal and insulator

The three basic ways a solid treats electricity, set by how its electrons fill the energies open to them. In a metal they fill a band of energies only partly, so the smallest push sets them moving, and it conducts at any temperature. In an insulator they fill a band completely and a wide gap separates it from the next, so nothing can move. A semimetal sits in between: two bands just touch or overlap a little, leaving a small number of mobile electrons and holes. NbSe₂ is a metal, graphene a semimetal, hBN an insulator.

A classification by where the Fermi level falls in the band structure. In a metal it crosses a partly filled band, leaving a Fermi surface, a carrier density of order one per atom (about 10²² cm⁻³) and a resistivity that falls on cooling. In a band insulator it lies in a gap of several electronvolts; a semiconductor is an insulator whose gap is small enough to be doped or gated. A semimetal has a slight overlap between conduction and valence bands (graphite, bismuth, bulk WTe₂) or bands that touch at isolated points (graphene), giving low and nearly equal densities of electrons and holes. Interactions can open gaps that band theory does not predict: Mott insulators from half-filled bands, excitonic insulators from semimetals.

Full explanation

Dielectric screening

The way a material weakens the pull between two charges inside it: its own electrons shift slightly and partly cancel the field between them. A sheet one atom thick has almost nothing around it to do this, so charges in it attract each other far more strongly than in a thick crystal – which is why light makes tightly bound pairs in 2D materials, and why whatever a sheet rests on changes its properties.

The reduction of the Coulomb interaction by the polarisation of bound electrons and ions and, in metals and doped layers, by free carriers, described by a dielectric function ε(q, ω). In a monolayer the field lines between distant charges run through the surroundings, so ε(q) approaches 1 as q → 0 and the screening is non-local and set by the environment. Exciton binding energies reach hundreds of meV, and a change of substrate or encapsulation shifts the quasiparticle gap by 100 meV or more while the optical gap barely moves.

Full explanation

Gating

Changing a material by putting a voltage on a nearby electrode – a gate – separated from it by an insulator. The voltage pulls electrons into the material or pushes them out, as in every transistor. Because a 2D material is so thin, the gate reaches all of it, so the number of electrons can be dialled up and down continuously: a single device can be turned from insulator to metal, its magnetism strengthened, or superconductivity switched on. Two gates, above and below, can also apply an electric field across the layer.

Electrostatic control of carrier density and electric field through a gate coupled capacitively across a dielectric: the induced density equals the gate capacitance times the voltage beyond threshold, divided by the electron charge, reaching a few 10¹³ cm⁻² with oxide or hBN gates before breakdown. Dual gating sets density and perpendicular displacement field independently, opening the gap of bilayer graphene and tuning moiré flat bands. Ionic-liquid and solid-electrolyte gating form an electric double layer about a nanometre thick and reach 10¹⁴–10¹⁵ cm⁻², enough to induce superconductivity in MoS₂ or raise the Curie temperature of Fe₃GeTe₂, but can intercalate or react electrochemically and work only while the ions are mobile. Hysteresis from traps, contact effects and quantum capacitance are the usual caveats.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Atomic layer deposition (ALD)

A way to coat a surface one layer of atoms at a time. Two chemicals take turns: the first sticks to every free spot on the surface but not to itself, the excess is pumped away, and the second reacts with what stuck, leaving one thin layer of, say, aluminium oxide. Repeating the pair builds the film with a precision of a fraction of a nanometre, even over deep, steep structures. It is how the gate insulators of modern computer chips are made – and on 2D materials it runs into a problem: their clean surfaces give the first chemical nothing to stick to.

Thin-film growth by alternating, self-limiting surface reactions of two precursors separated by purges – for Al₂O₃ trimethylaluminium and water, for HfO₂ a hafnium amide or chloride with water or ozone – typically at 100 to 300 °C, giving about 0.1 nm per cycle with sub-nanometre control and conformal coverage. It is the standard route to high-κ gate dielectrics in silicon CMOS. On the dangling-bond-free basal planes of graphene, TMDCs and hBN the first precursor finds no reactive sites, so nucleation starts only at steps, defects and residues, giving islands and pinholes. Seed layers (evaporated and oxidised Al, molecular layers), ozone or plasma functionalisation, low-temperature physisorption, or transferred and native-oxide dielectrics are used instead, each at a cost in thickness, interface traps or channel damage.

Full explanation

Band alignment

How the energy levels of two materials line up when they are put together: whether one material’s electrons sit above or below the other’s. Electrons roll ‘downhill’ to the lower level, so the alignment decides which way charge moves across the junction, and so decides what the stack can be used for.

The relative positions of the band edges of two materials in contact, classified as straddling (type I), staggered (type II) or broken (type III). Van der Waals stacking avoids chemical bonding and strain, so alignments start close to the isolated layers’ ionisation potentials and electron affinities, shifted by interface dipoles and by the dielectric environment. A type-II alignment puts electron and hole in different layers, which is what makes interlayer excitons and gate-tunable photovoltaic junctions possible.

Full explanation