Atomic layer deposition (ALD)

In plain words

A way to coat a surface one layer of atoms at a time. Two chemicals take turns: the first sticks to every free spot on the surface but not to itself, the excess is pumped away, and the second reacts with what stuck, leaving one thin layer of, say, aluminium oxide. Repeating the pair builds the film with a precision of a fraction of a nanometre, even over deep, steep structures. It is how the of modern computer chips are made – and on it runs into a problem: their clean surfaces give the first chemical nothing to stick to.

Going deeper

Two gases take turns, each reacting only with what the other left behind, so every cycle adds one thin layer and the film coats even deep trenches evenly. On the clean face of a 2D material there is nothing for the first gas to bind to, so the oxide starts only at edges and defects and grows as islands with pinholes between them.

One layer at a time

Each cycle has four steps. The first precursor – for aluminium oxide, trimethylaluminium – flows in and reacts with the hydroxyl groups on the surface until every site is taken; because it does not react with itself, the reaction then stops. A purge sweeps away the excess. Water flows in next, reacts with what the first precursor left on the surface and leaves a fresh layer of hydroxyl groups, ready for the next cycle; a second purge clears the by-products. Each cycle adds roughly a tenth of a nanometre, so the thickness is set by counting cycles.

Because each step stops by itself, the film follows every contour of the surface and coats the walls of deep trenches as evenly as the top. That is why ALD has supplied the hafnium oxide gate insulators of silicon since the 45-nanometre generation, and why it is the first choice for putting a gate on a 2D channel.

Nothing to stick to

On a 2D material the first step fails. The basal plane of graphene, MoS₂ or hBN has no and no hydroxyl groups, so the precursor finds nowhere to react except at edges, steps, defects and leftover polymer. Growth starts as scattered islands that merge late, leaving pinholes and a rough film that leaks; on pristine graphene, early experiments found oxide growing only along edges and defects.

The remedies all trade something. A nanometre of aluminium evaporated and oxidised first gives the precursor a surface but adds thickness and charge; molecular seed layers or a brief ozone or plasma treatment create reactive sites but can damage or dope the channel; growth at low temperature lets the precursor stick physically but gives a poorer oxide. Other routes avoid ALD on the channel altogether: hBN, crystalline fluorides such as CaF₂, or oxides grown from the material itself, such as Bi₂SeO₅ on Bi₂O₂Se.

What to check

The gate insulator decides much of how a 2D transistor behaves: pinholes cause leakage, charge trapped in the oxide or at the interface causes and threshold shifts, and the process itself can dope or damage the channel. A film that looks continuous in an optical microscope can still be full of pinholes, so leakage maps, and transmission electron cross-sections are the usual checks, together with the characteristics of the same transistor measured before and after the deposition.

For specialists

Thin-film growth by alternating, self-limiting surface reactions of two precursors separated by purges – for Al₂O₃ trimethylaluminium and water, for HfO₂ a hafnium amide or chloride with water or ozone – typically at 100 to 300 °C, giving about 0.1 nm per cycle with sub-nanometre control and conformal coverage. It is the standard route to gate dielectrics in silicon . On the dangling-bond-free basal planes of graphene, and hBN the first precursor finds no reactive sites, so nucleation starts only at steps, defects and residues, giving islands and pinholes. Seed layers (evaporated and oxidised Al, molecular layers), ozone or plasma functionalisation, low-temperature physisorption, or transferred and native-oxide dielectrics are used instead, each at a cost in thickness, or channel damage.

Where this comes from

Atomic layer deposition: an overview George · Chemical Reviews 110, 111 (2010)
Atomic layer deposition of metal oxides on pristine and functionalized graphene Wang et al. · Journal of the American Chemical Society 130, 8152 (2008)
Insulators for 2D nanoelectronics: the gap to bridge Illarionov et al. · Nature Communications 11, 3385 (2020) cited by 559

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Dangling bond

A bond left with nothing on the other end, on an atom at a surface that has lost the neighbour it was bonded to inside the crystal. Such bonds grab stray molecules and trap electrons, which is why ordinary surfaces are messy – and why layered crystals, whose sheets keep every bond inside themselves, split into faces that stay clean down to a single layer.

An unsaturated valence orbital at a surface, edge or defect where a covalent bond has been cut. In a bulk semiconductor such as silicon these states lie in the gap, trap charge and pin the Fermi level unless passivated by hydrogen or a grown oxide. The basal plane of a layered crystal has none, which is what allows van der Waals stacking without lattice matching and interfaces with few traps – and also why atomic layer deposition nucleates poorly on it. Edges, grain boundaries and vacancies do carry them, and are where 2D materials are chemically active.

Full explanation

Layer transfer

Moving an atomically thin layer from where it was made to where it is needed – from the copper foil it grew on to a silicon wafer, or from a flake on tape onto another flake. The layer is too thin to pick up on its own, so it is carried on a polymer film or a soft stamp, put down, and the carrier removed. Each step risks tears, wrinkles, trapped bubbles and a film of leftover polymer, which is why transfer is often the dirtiest step in making a 2D device.

The step that moves a 2D layer from its growth substrate or exfoliation source to a target substrate or stack. Wet transfer coats the layer with a supporting polymer, usually PMMA, detaches it by etching the growth substrate or by electrochemical bubbling, and floats it onto the target before the polymer is dissolved. Dry transfer picks layers up with a viscoelastic PDMS stamp or a polymer film such as polycarbonate, often using the van der Waals adhesion of a top flake, and releases them by heating. The costs are cracks and wrinkles, trapped water, hydrocarbons and polymer residue, strain and doping, and – at wafer scale – yield that compounds with every transfer, which is why growth directly on the target and transfer-free routes are pursued.

Full explanation

Complementary metal–oxide–semiconductor (CMOS)

The way almost every digital chip is built. Each logic gate pairs a transistor that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A 2D material becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.

Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, threshold voltages held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for back-end-of-line integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe₂ is the leading p-type candidate.

Full explanation