Engineering track · for people deciding what to build
Engineering, manufacturing & industry
For process and device engineers, product developers and technical decision-makers deciding whether a 2D material belongs on a roadmap. The focus is readiness rather than records: what is shipping, what is blocked and by what, how integration with existing manufacturing works, and which heuristics separate a viable application from a press release.
17 technologies rated10 manufacturing problems15 companies and institutes11 rules of thumb
This page is written for specialists. For a plain-language introduction, start with the basics.
You are reading as a theoretician. This is the engineering track; the theory track is the one written for you.
You are reading as an experimentalist. This is the engineering track; the experiment track is the one written for you.
A chip is built in two stages: transistors first, in and on the silicon, then many levels of metal wiring above them. Everything in the second stage has to happen below roughly 400 °C, which is the central constraint on putting 2D materials into a real process. FEOL and BEOL in the glossary →
How ready each technology is
17 technologies, each with the level it has reached, the reasoning behind that level, and the one thing holding it back.
Technology readiness level reached by each technology, from 1 (the principle observed) to 9 (proven in routine use). Select a name for the reasoning, the blocking issue and who is working on it.
How the levels are counted follow the EU Horizon scale: 1–3 basic principles to proof of concept; 4 validated in the lab; 5 validated in a relevant environment; 6 demonstrated in a relevant environment; 7 prototype in an operational environment; 8 complete and qualified system; 9 proven in operational use.
In use today · 6
TRL 8–9: qualified systems, sold and running in the field.
Graphene-enhanced composites, coatings and additives
research
development
deployment
TRL 9 · proven in operational use
Why that level
Products containing graphene-related powders are sold in volume – sports goods, tyres, and concrete additives – so the technology is in operational use, even though performance benefits and actual graphene content vary widely.
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What is blocking it
Quality variability and weak differentiation; standards for specifying graphene content are only now entering procurement.
Outlook
Steady, incremental growth; differentiation will increasingly depend on certified material quality.
Who is working on it
Many powder producers and formulators worldwide, supplying consumer and industrial brands
Graphene-based heat-spreading films
research
development
deployment
TRL 9 · proven in operational use
Why that level
Graphene-based films have shipped in smartphones since 2018 (for example the Huawei Mate 20 X), with established production.
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What is blocking it
Competition from highly oriented pyrolytic graphite films on cost versus performance.
Outlook
Demand rises with thermal loads in phones, laptops and AI hardware.
Who is working on it
Film producers, mainly in China
Graphene Hall-effect magnetic sensors
research
development
deployment
TRL 9 · proven in operational use
Why that level
Graphene made by transfer-free growth on are sold commercially and used in scientific and industrial instruments, including cryogenic high-field measurement.
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What is blocking it
Niche volumes; mass markets are served by mature silicon, GaAs and InSb sensors, which set a hard cost target.
Outlook
Expansion into monitoring, quantum-computing infrastructure and high-field instrumentation.
Who is working on it
Paragraf (UK)
Graphene quantum Hall resistance standards
research
development
deployment
TRL 8 · complete and qualified system
Why that level
graphene on SiC realises the resistance at higher temperatures and lower magnetic fields than GaAs devices, and is used by national metrology institutes.
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What is blocking it
Small market; device yield and long-term stability of .
Outlook
Wider dissemination of primary resistance standards beyond national laboratories.
Who is working on it
National metrology institutes and epitaxial-graphene suppliers
Supercapacitors with graphene-based carbon electrodes
research
development
deployment
TRL 9 · proven in operational use
Why that level
Commercial using graphene-related carbon materials are in service in grid, transport and data-centre power systems.
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What is blocking it
Energy density remains far below batteries; the active material is a graphene-like carbon, not graphene.
Outlook
Growth in power smoothing for AI data centres and in grid services.
Who is working on it
Skeleton Technologies (Estonia and Germany)
Graphene conductive additives in lithium-ion cells
research
development
deployment
TRL 9 · proven in operational use
Why that level
Graphene-containing conductive pastes are used in commercial cell manufacturing, mainly in China.
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What is blocking it
Cost and dispersion quality compared with carbon black and carbon nanotube additives.
Outlook
Most useful in fast-charging and high-power cells; carbon nanotubes are the main competitor.
Who is working on it
Powder and paste producers supplying cell manufacturers
Out of the lab, not yet routine · 5
TRL 5–7: validated or demonstrated in a realistic environment, sometimes as a prototype in service.
Graphene photonics for optical interconnects
research
development
deployment
TRL 5 · validated in a relevant environment
Why that level
Wafer-scale graphene have been fabricated with -compatible methods (Graphenea and imec, ~15 GHz bandwidth), and a dedicated 300 mm graphene-photonics pilot line is being built in Aachen, with pilot production planned for 2027.
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No qualified product yet.
What is blocking it
Uniform, low-defect graphene on 300 mm photonic wafers; ; device-to-device variation and reliability.
Outlook
A credible candidate for energy-efficient optical links in AI data centres if wafer-level yield is proven.
Who is working on it
Black (Germany), Graphenea and imec within the EU 2D Pilot Line, and research groups
MXene electromagnetic shielding coatings
research
development
deployment
TRL 5 · validated in a relevant environment
Why that level
performance is extensively validated in laboratory films and prototype coatings (~92 dB for a 45 µm Ti3C2Tx film), but no product has been qualified, and oxidation stability over a product lifetime is unproven.
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What is blocking it
Oxidation in storage and use, fluoride-based synthesis, and supply of high-purity precursors.
Outlook
Niche uses in aerospace, defence and flexible electronics are plausible within several years if stability is solved.
Who is working on it
Academic groups and specialist MXene suppliers
Graphene neural interfaces
research
development
deployment
TRL 6 · demonstrated in a relevant environment
Why that level
A graphene cortical interface was used in a first-in-human study in Manchester (first procedure 2024, enrolment completed 2026); no regulatory approval yet.
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What is blocking it
Long-term implant reliability, the regulatory pathway, and manufacturing under medical-device quality systems.
Outlook
Temporary intraoperative mapping is likely to reach patients before chronic implants.
Who is working on it
INBRAIN Neuroelectronics (Spain) with clinical and academic partners
Graphene transparent conductive films
research
development
deployment
TRL 6 · demonstrated in a relevant environment
Why that level
Working touch panels were demonstrated from graphene in 2010, but graphene has not become competitive with ITO, silver nanowires or metal mesh.
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What is blocking it
The trade-off between and transparency, stability of doping, and cost per square metre.
Outlook
Unlikely to win mainstream displays; possible niches in flexible or harsh-environment electrodes.
Who is working on it
Film producers and research groups
2D perovskite passivation layers in perovskite photovoltaics
research
development
deployment
TRL 6 · demonstrated in a relevant environment
Why that level
Widely used in high-efficiency research cells and in module-scale development of perovskite and perovskite–silicon tandem .
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What is blocking it
Long-term field stability of perovskite modules as a whole, and lead management.
Outlook
Its fate is tied to the commercial success of perovskite photovoltaics.
Who is working on it
Perovskite PV developers and research groups
Still proving the concept · 6
TRL 1–4: principles, proofs of concept and lab validation.
2D-channel transistors for advanced logic
research
development
deployment
TRL 4 · validated in the lab
Why that level
and test structures have been integrated on 300 mm wafers in industrial research fabs (imec showed a 300 mm WS2-integrated wafer in 2025), and an academic 32-bit microprocessor with 5,900 MoS2 transistors ran in 2025 – but no process has been validated for yield, variability and reliability at product level.
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What is blocking it
Contact resistance, devices, defect density and uniformity over 300 mm, integration, and growth within process .
Outlook
Roadmaps treat 2D channels as an option for the 2030s, most likely first in stacked transistor architectures.
Who is working on it
imec and major chipmakers publishing at IEDM and VLSI, together with academic groups
2D devices in the back end of line and monolithic 3D circuits
research
development
deployment
TRL 3 · experimental proof of concept
Why that level
Low-temperature 2D transistors and sensors built on top of finished CMOS have been demonstrated in research; there is no qualified back-end process.
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What is blocking it
Growing or transferring films below ~400–450 °C with adequate and uniformity.
Outlook
Attractive for sensors, memory selectors and additional logic layers stacked on CMOS.
Who is working on it
Research institutes and university groups
hBN as a manufacturable dielectric and encapsulant
research
development
deployment
TRL 3 · experimental proof of concept
Why that level
hBN is essential in laboratory devices, but wafer-scale, low-defect films deposited (rather than hand-stacked) into devices remain at proof-of-concept level.
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What is blocking it
Growth temperature, film uniformity, leakage and dielectric reliability statistics.
Outlook
Likelier first as an interface or layer than as the bulk .
Who is working on it
Research institutes, equipment makers and academic groups
2D memristors and neuromorphic devices
research
development
deployment
TRL 3 · experimental proof of concept
Why that level
Single devices and small crossbar arrays demonstrated; oxide-based resistive memory is already in production and sets the benchmark.
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What is blocking it
Variability, endurance and retention statistics at array scale.
Outlook
Must beat mature oxide RRAM on a clearly defined metric to justify adoption.
Who is working on it
Academic groups and research institutes
2D membranes for water and molecular separation
research
development
deployment
TRL 4 · validated in the lab
Why that level
Laboratory are well validated; larger modules and field trials are at an early stage, and no 2D membrane has displaced commercial reverse-osmosis membranes.
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What is blocking it
Defect-free large areas, swelling of graphene-oxide laminates, fouling, and cost against mature polyamide membranes.
Outlook
Niche separations such as solvent recovery or selective ion removal are likelier first targets than seawater desalination.
Who is working on it
Academic groups and small companies
hBN single-photon sources and spin-defect sensors
research
development
deployment
TRL 3 · experimental proof of concept
Why that level
Room-temperature emitters and optically addressable defects are demonstrated, but deterministic placement and reproducible emission wavelengths are not.
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What is blocking it
Emitter reproducibility, placement and integration with photonic circuits.
Outlook
Research-stage, competing with and colour centres in diamond and SiC.
Who is working on it
Academic groups and quantum-technology programmes
What manufacturing has to solve
10 problems that stand between a laboratory result and a production line, with the best that has been managed so far.
Each manufacturing problem, the best managed so far, and what it would take
Problem
Best so far
What it would take
Wafer-scale growth scatter carriers, and single-orientation growth needs epitaxial templates – vicinal sapphire, Cu(111) – that are not the wafers devices are built on.
Single-orientation MoS2 on vicinal sapphire and single-crystal graphene on Cu(111) in research; polycrystalline films on 200–300 mm wafers in industrial labs.
Single-crystal growth directly on CMOS-compatible , or damage-free wafer-level transfer.
Transfer without damage or contaminationPolymer residues, cracks, wrinkles and metal contamination all scale with area, and fabs forbid many of the chemicals used in laboratory transfer.
with temporary adhesives in industrial research fabs; transfer-free epitaxial graphene on SiC.
Fab-qualified, residue-free bonding and debonding – or direct growth within back-end thermal budgets.
Contact resistance, and deposition damage; a monolayer has no bulk beneath the contact that can be heavily doped.
42 Ω·µm with antimony on MoS2 (2023), which melts at 631 °C rather than bismuth’s 271 °C; p-type contacts remain far worse.
Contacts below ~100 Ω·µm for p-type devices as well, in a metallurgy and process a fab accepts.
Doping control and p-type devicesSubstitutional doping during growth is hard to control, surface is unstable, and p-type contacts to WSe2 lag behind n-type contacts to MoS2.
Substitutional and charge-transfer doping demonstrated in research; high-work-function metals for p-type contacts.
Stable, localised doping for source and drain regions compatible with downstream processing.
Gate dielectrics on inert basal planesWithout , does not nucleate uniformly; seed layers add thickness and .
Seed layers, low-temperature ALD, molecular-crystal and hBN dielectrics in research – interface trap densities are still above silicon benchmarks.
Sub-nanometre equivalent oxide thickness with interface trap densities near 1010 cm−2 eV−1 on 2D channels.
Thermal budgetThe best films grow at roughly 600–900 °C, while back-end processing is limited to about 400–450 °C, and front-end integration must survive every later high-temperature step.
Low-temperature MOCVD with reduced crystallinity; PtSe2 selenisation at ~400 °C; transfer of films grown hot elsewhere.
Highly crystalline growth at low temperature, or reliable transfer at wafer scale.
Metrology and in-line inspectionLayer number, defects, grain orientation and contamination must be measured quickly and non-destructively across 300 mm wafers.
and mapping, spectroscopic ellipsometry and automated optical inspection; slow and for defect identification.
High-throughput defect and grain metrology that correlates with electrical yield.
Uniformity and variabilityOne extra layer is a 100% thickness error, and depends on local defects and doping.
Wafer maps of mobility and threshold voltage over hundreds to thousands of research devices.
Threshold-voltage variation of tens of millivolts or less across full wafers, under .
ReliabilityData on bias-temperature instability, , dielectric breakdown and interface in 2D stacks are sparse.
Early reliability studies of MoS2 transistors with high- dielectrics.
Standardised, industry-style reliability qualification data sets for 2D device stacks.
Specifying powders and Material sold as graphene ranges from monolayer to ground graphite, so a name is not a specification.
International standards for graphene powders and dispersions – ISO/TS 21356-1:2021 and ISO/TS 23359:2025 for characterising them, ISO/TS 9651:2025 for classifying them with a common datasheet – and supplier datasheets.
Routine use of standards in procurement, with third-party verification of batches.
Fitting into a silicon fab
Why chipmakers are looking at 2D channels at all, what a fab demands before one can be used, and the routes being tried.
As silicon channels are thinned below a few nanometres, carrier mobility drops and short-channel control worsens. A 2D semiconductor is under a nanometre thick with no dangling bonds, so it may preserve electrostatic control in the thinnest channels – which is why chipmakers study for the far end of the silicon roadmap.
What the fab requires · 6
Thermal budget of roughly 400–450 °C for back-end processing; front-end integration must survive subsequent high-temperature steps
Contamination rules: no alkali metals, restricted metal species and no organic residues in shared tools
Uniformity and yield statistics across 300 mm wafers
Low contact resistance for both n- and p-type devices
Dielectric integration with low interface trap density
Compatibility with and stacked complementary transistor architectures
Only a process that stays under about 450 °C can run on a wafer that already carries finished transistors. Of the methods here, that leaves peeling and wet chemistry, which give flakes rather than films, and converting a platinum film into PtSe₂ at about 400 °C. The other ways of growing a film start at 500 °C or more, which is why the first route below grows the layer elsewhere and transfers it. Temperatures are from each method’s typical conditions on the Experiment page; liquid exfoliation, flux growth and MBE state none, so they are not shown.
How a 2D layer gets in · 4
Growth elsewhere, then transfer of MOCVD films onto 300 mm wafers
Demonstrated in industrial research fabs
High growth quality, but transfer defects and contamination risks
Direct low-temperature growth on the target wafer
Research
Avoids transfer, at the cost of crystallinity and mobility
2D layers added in the back end of line (monolithic 3D)
Research prototypes
Adds functions on top of finished CMOS, under strict thermal limits
2D channels in stacked nanosheet or complementary FET architectures
Roadmap concept
The largest potential benefit and the hardest integration
On roadmap datesPublic industry roadmaps list 2D channel materials as options for the 2030s rather than for current nodes. Treat any specific insertion date as a planning scenario, not a commitment.
Where the material comes from
7 inputs a 2D product depends on, how each is supplied today, and what that exposes you to.
The 7 inputs below, marked where each one's text names the exposure; a name under a mark says which part of the input it applies to. A blank means the text does not say, not that the risk is absent. Select an input for its situation.
High-quality hBN crystals
The best crystals come from a small number of growers, most prominently Japan’s National Institute for Materials Science; flux-grown alternatives are expanding supply.
The exposureResearch depends on a few suppliers, and wafer-scale hBN as good as exfoliated crystals is not yet available.
Natural graphite
The EU and US classify graphite as critical; China dominates processing and introduced export licensing for certain graphite products at the end of 2023. Stricter controls on graphite anode materials announced in October 2025, and tighter licensing for exports to the United States, are suspended until November 2026.
The exposurePrice and access volatility for graphene-related powder feedstocks and battery anodes.
Tungsten and molybdenum
Tungsten is on the EU list, and molybdenum mining is concentrated in a few countries. Since February 2025 China, the largest tungsten producer, has required export licences for tungsten and molybdenum products, and for tellurium, bismuth and indium as well.
The exposureFor MOCVD precursors, purity requirements usually matter more than metal price, but export licensing can now delay supply.
Chalcogen precursors
H2S and H2Se are highly toxic, and tellurium is a by-product of copper refining with limited supply, now under Chinese export licensing.
The exposureSafety infrastructure costs, and supply constraints for telluride-based materials.
MAX-phase powders and fluoride chemistry
MXene scale-up depends on high-purity MAX phases and on handling HF or fluoride salts. Fluorspar, the mineral both are made from, is on the EU critical raw materials list.
The exposureFew suppliers and a significant environmental, health and safety burden.
Borates
Boron, mined as borates, is on the EU critical raw materials list.
The exposureFeedstock exposure for hBN and other boron-based materials.
Specialty substrates
SiC wafers for epitaxial graphene and sapphire for TMDC epitaxy; SiC capacity is driven by power electronics.
The exposureSubstrate cost, though SiC wafer prices have fallen since 2024 as capacity grew faster than demand.
Who is building this
15 companies, suppliers and institutes whose business is 2D materials, as a starting point for finding partners rather than a market survey.
The 15 organisations below, by where they are based: a starting list for finding partners, not a count of the industry. Select a name for what it does.
Vocabulary for graphene and other 2D materials (ISO/TS 80004-13:2024), a classification framework with a common datasheet template (ISO/TS 9651:2025), and characterisation standards for graphene powders and dispersions: ISO/TS 21356-1:2021 for structure and ISO/TS 23359:2025 for chemistry
Defines what may be called graphene and how to measure it – the basis of material specifications
Pilot line within the Graphene Flagship initiative that integrates graphene and TMDCs into silicon photonics and electronics, offering multi-project wafer runs to companies and researchers; coordinated by imec and running until 2028
State-aid framework for large cross-border microelectronics projects; Germany and North Rhine-Westphalia committed €228.7 million to Black Semiconductor’s graphene-photonics pilot line under it
Federal semiconductor manufacturing incentives and R&D programmes run from NIST; since August 2025 NIST operates the National Semiconductor Technology Center itself, after the Commerce Department voided its agreement with Natcast, the operator chosen in January 2025
Rules of thumb
11 heuristics that separate an application worth funding from one that only reads well.
If it works with graphite, ask whether it really needs graphene.Many composite, thermal and battery benefits come from thin, well-dispersed platelets; paying for true monolayers rarely pays back.
Specify distributions, not names.Layer-number and lateral-size distributions, C/O ratio and impurity levels determine performance – ‘graphene’ on its own specifies nothing.
Budget for the contact, not just the channel.In short-channel 2D transistors, contact resistance often dominates total device resistance.
Never design around champion devices.Medians and spreads from tens to hundreds of devices predict yield; best-case numbers do not.
Every transfer step multiplies yield by a number below one.Losses compound across stacked layers, so minimise transfers or grow directly.
Check the thermal budget before the mobility.A process that needs 800 °C cannot enter the back end of line, whatever its electrical performance.
Assume air changes the device until proven otherwise.For most TMDCs and all tellurides, encapsulation and inert handling belong in the process flow from the start.
Qualify the batch, not just the supplier.Batch-to-batch variation in 2D materials is large; incoming inspection has to be routine.
Benchmark against the incumbent’s roadmap, not its current product.Silicon, ITO, carbon black and polymer membranes keep improving; the gap to beat will be larger at launch.
Start where there is no incumbent, or where the incumbent fails.Early 2D successes – cryogenic high-field Hall sensors, thin heat spreaders – filled gaps rather than displacing established parts.
Plan for regulation early.Nanoform registration under REACH, occupational exposure limits and medical-device rules add time and cost that surprise late movers.
Searches to follow
12 standing arXiv searches for this track. They are part of what fills this site’s news feed, and each link opens the live feed from the arXiv API for a feed reader to subscribe to; the query itself is written out so you can change it.
2D transistors (applied physics)
Device engineering of 2D-channel transistors
cat:physics.app-ph AND (abs:transistor OR abs:FET) AND (abs:MoS2 OR abs:WSe2 OR abs:"two-dimensional semiconductor")
(abs:"wafer-scale" OR abs:"wafer scale" OR abs:"300 mm") AND (abs:MoS2 OR abs:graphene OR abs:"transition metal dichalcogenide" OR abs:"two-dimensional")
CMOS integration, back end of line and monolithic 3D
Integrating 2D devices with or on top of CMOS – broadened with CMOS-compatible and monolithic-integration terms because back-end-of-line terms alone returned too few papers
(abs:"back-end-of-line" OR abs:BEOL OR abs:"monolithic 3D" OR abs:"monolithic three-dimensional" OR abs:"CMOS-compatible" OR abs:"monolithic integration") AND (abs:MoS2 OR abs:WSe2 OR abs:"2D material" OR abs:"two-dimensional material" OR abs:"transition metal dichalcogenide")
Separation-specific terms only: the bare word membrane mostly matches suspended optomechanical resonators in physics categories. arXiv coverage of this field is thin because most 2D-membrane work appears in chemistry journals, so expect a sparse feed
(abs:desalination OR abs:"ion sieving" OR abs:"molecular sieving" OR abs:nanofiltration OR abs:"gas separation" OR abs:"water permeation" OR abs:"ion selectivity" OR abs:"proton transport") AND (abs:graphene OR abs:"graphene oxide" OR abs:MXene OR abs:"hexagonal boron nitride" OR abs:MoS2 OR abs:"two-dimensional material")
Hexagonal boron nitride (hBN) is a material with excellent insulating properties that make it well-suited as a gate dielectric in 2D electronic devices. In recent years, the discovery of an ever-increasing list of properties has led to a much broader range of potential applications, including quantum…
Researchers at Dongguk University in South Korea have developed a battery-free, flexible graphene transistor that mimics biological synapses and can recognize human activity without any external power source. A self-powered graphene-channel transistor, driven entirely by triboelectric nanogenerators, mimics biological…
We investigate the nanoscale mechanisms determining in-plane lattice (LTC) of pristine and W-doped MX –M X transition metal dichalcogenide from , using the exact solution of the linearised Boltzmann transport equation in both and relaxon bases. For the W-doped…
nitrate reduction can couple nitrate removal with ammonia recovery. Successive hydrogenation steps require a local supply of proton equivalents, but making water-derived hydrogen available at nitrate-reduction sites remains difficult. Here, CuCo-LDH supported on anatase TiO2 nanosheets (CuCo-LDH@TNS) is…
Two-dimensional materials are promising candidates for electronic applications beyond the operating limits of conventional semiconductor technologies. Within this class, transition-metal dichalcogenides offer attractive properties for field-effect transistor operation, with tungsten disulphide (WS2) emerging as a…
The worldwide graphene flake productionKauling et al. · Advanced Materials 30, 1803784 (2018)cited by 368Required reading before buying any graphene powder.