Interface trap density (Dit)

In plain words

How many electrical ‘traps’ sit at the boundary between a ’s channel and its . Traps catch and release charge, which makes switching slower, noisier and less predictable.

Going deeper

Dit counts the electronic states sitting at the channel–dielectric boundary, per unit area and per electronvolt. Every one of them can catch a carrier and let it go again, which is why the same number shows up in the switching slope, in hysteresis and in low-frequency noise.

What a trap does

A trap is a state whose energy falls inside the channel’s and whose wavefunction sits at or near the interface. As the gate sweeps the channel’s bands past it, the state fills and empties. Because that filling takes time – from nanoseconds to seconds, depending on how far the trap sits from the band edge and how far it is from the channel – the charge in the traps lags the gate.

Everything unpleasant follows from that lag. Charge stored in traps screens part of the gate’s field, so more voltage is needed per decade of current. Charge that is still trapped when the sweep reverses shifts the threshold, which is . Traps that capture and emit at random produce the low-frequency noise that dominates small transistors.

Why 2D channels make it harder

The silicon industry solved this problem once, with a thermally grown oxide whose interface can be pushed to roughly ten to the tenth states per square centimetre and electronvolt, helped along by hydrogen . None of that transfers. A 2D crystal has no , which is exactly why an amorphous oxide will not nucleate uniformly on it: tends to start at defects and step edges, leaving a rough, pinhole-prone layer with an ill-defined boundary.

The alternatives each have a catch. Hexagonal boron nitride gives a clean interface but has a low and leaks at the thicknesses that would be needed. Native oxides of the 2D itself, seeded oxides, and crystalline fluorides are all being tried. The field sums it up itself: the lack of a scalable , not the channel, is what keeps 2D transistors short of their predicted performance.

Reading a quoted number

Dit is extracted, not observed. The subthreshold slope gives the quickest estimate, but it lumps in everything else that slows switching, so it is an upper bound. Capacitance– and conductance–voltage methods across a range of frequencies separate traps by their time constants and are more informative, though they need a well-behaved capacitor, which is itself hard to make on a 2D channel.

So a bare number means little. A useful one comes with the method, the temperature, the sweep rate and the gate range used, because slow traps simply do not respond to a fast sweep and drop out of the count unnoticed. Comparing two papers that used different sweep rates is comparing two different subsets of the same defects.

For specialists

The density of electronic states at the channel–dielectric interface that capture charge, degrading switching and stability.

Where this comes from

Insulators for 2D nanoelectronics: the gap to bridge Illarionov et al. · Nature Communications 11, 3385 (2020) cited by 559

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Passivation

Treating a surface so that it stops reacting with its surroundings and stops trapping electrons – by covering it with a thin protective layer, or by attaching atoms that tie up its loose bonds. Aluminium does it by itself: a skin of oxide a few nanometres thick is why aluminium window frames do not corrode away. A 2D material is all surface, so passivating it can decide whether it glows brightly, conducts well or survives in air at all.

The chemical or physical deactivation of a surface or interface: saturating dangling bonds and trap states (hydrogen on silicon, sulfur on III–V surfaces), compensating defects (superacid or thiol treatment of TMDC vacancies), or sealing with a dielectric such as Al₂O₃ or hBN. In 2D semiconductors it raises photoluminescence yield, lowers interface trap density and hysteresis, and slows oxidation; in perovskite solar cells a thin 2D perovskite layer passivates the surface of the 3D absorber.

Full explanation

Dangling bond

A bond left with nothing on the other end, on an atom at a surface that has lost the neighbour it was bonded to inside the crystal. Such bonds grab stray molecules and trap electrons, which is why ordinary surfaces are messy – and why layered crystals, whose sheets keep every bond inside themselves, split into faces that stay clean down to a single layer.

An unsaturated valence orbital at a surface, edge or defect where a covalent bond has been cut. In a bulk semiconductor such as silicon these states lie in the gap, trap charge and pin the Fermi level unless passivated by hydrogen or a grown oxide. The basal plane of a layered crystal has none, which is what allows van der Waals stacking without lattice matching and interfaces with few traps – and also why atomic layer deposition nucleates poorly on it. Edges, grain boundaries and vacancies do carry them, and are where 2D materials are chemically active.

Full explanation

Atomic layer deposition (ALD)

A way to coat a surface one layer of atoms at a time. Two chemicals take turns: the first sticks to every free spot on the surface but not to itself, the excess is pumped away, and the second reacts with what stuck, leaving one thin layer of, say, aluminium oxide. Repeating the pair builds the film with a precision of a fraction of a nanometre, even over deep, steep structures. It is how the gate insulators of modern computer chips are made – and on 2D materials it runs into a problem: their clean surfaces give the first chemical nothing to stick to.

Thin-film growth by alternating, self-limiting surface reactions of two precursors separated by purges – for Al₂O₃ trimethylaluminium and water, for HfO₂ a hafnium amide or chloride with water or ozone – typically at 100 to 300 °C, giving about 0.1 nm per cycle with sub-nanometre control and conformal coverage. It is the standard route to high-κ gate dielectrics in silicon CMOS. On the dangling-bond-free basal planes of graphene, TMDCs and hBN the first precursor finds no reactive sites, so nucleation starts only at steps, defects and residues, giving islands and pinholes. Seed layers (evaporated and oxidised Al, molecular layers), ozone or plasma functionalisation, low-temperature physisorption, or transferred and native-oxide dielectrics are used instead, each at a cost in thickness, interface traps or channel damage.

Full explanation

Dielectric screening

The way a material weakens the pull between two charges inside it: its own electrons shift slightly and partly cancel the field between them. A sheet one atom thick has almost nothing around it to do this, so charges in it attract each other far more strongly than in a thick crystal – which is why light makes tightly bound pairs in 2D materials, and why whatever a sheet rests on changes its properties.

The reduction of the Coulomb interaction by the polarisation of bound electrons and ions and, in metals and doped layers, by free carriers, described by a dielectric function ε(q, ω). In a monolayer the field lines between distant charges run through the surroundings, so ε(q) approaches 1 as q → 0 and the screening is non-local and set by the environment. Exciton binding energies reach hundreds of meV, and a change of substrate or encapsulation shifts the quasiparticle gap by 100 meV or more while the optical gap barely moves.

Full explanation

Metal, semimetal and insulator

The three basic ways a solid treats electricity, set by how its electrons fill the energies open to them. In a metal they fill a band of energies only partly, so the smallest push sets them moving, and it conducts at any temperature. In an insulator they fill a band completely and a wide gap separates it from the next, so nothing can move. A semimetal sits in between: two bands just touch or overlap a little, leaving a small number of mobile electrons and holes. NbSe₂ is a metal, graphene a semimetal, hBN an insulator.

A classification by where the Fermi level falls in the band structure. In a metal it crosses a partly filled band, leaving a Fermi surface, a carrier density of order one per atom (about 10²² cm⁻³) and a resistivity that falls on cooling. In a band insulator it lies in a gap of several electronvolts; a semiconductor is an insulator whose gap is small enough to be doped or gated. A semimetal has a slight overlap between conduction and valence bands (graphite, bismuth, bulk WTe₂) or bands that touch at isolated points (graphene), giving low and nearly equal densities of electrons and holes. Interactions can open gaps that band theory does not predict: Mott insulators from half-filled bands, excitonic insulators from semimetals.

Full explanation