Multi-project wafer (MPW) run

In plain words

A shared production run in which designs from several companies or labs are made on the same , so each pays only a fraction of the cost.

Going deeper

A multi-project wafer puts several customers’ designs into one reticle and runs them together. Each pays a share of the mask set and the run, which is the difference between a prototype costing a few tens of thousands and a few millions.

Sharing the expensive part

Almost all of the cost of a small production run is fixed. The mask set for an advanced node runs to millions, and it buys the same masks whether one wafer is exposed or ten thousand. For anyone wanting a few hundred chips – a research group, a start-up, a company testing an idea – that arithmetic is prohibitive.

A multi-project wafer, also called a shuttle, divides the reticle field among several customers. Each design occupies a block; the wafer is processed once; the wafer is diced and each customer receives their own dies, typically a few dozen packaged parts. The service model goes back to MOSIS in the early 1980s, and every major foundry and several national programmes now run scheduled shuttles for their process nodes.

What you give up

Everything about a shuttle is fixed in advance. The dates are fixed, so a design either makes the deadline or waits for the next slot months later. The process is fixed to the foundry’s qualified flow, described by a process design kit, and nothing about it can be adjusted for one customer on a shared wafer. The area is small and expensive per square millimetre, which shapes what can be attempted.

The shared nature has its own consequences: a yield problem affects everyone on the wafer, and the design rules are enforced strictly, because a violation in one block can compromise the run. A shuttle is a prototyping service, not a production route – moving to volume means a dedicated mask set eventually, with the qualification work that implies.

Where a 2D device would fit

For 2D electronics this is the point at which the research meets an industrial reality. A shuttle runs the foundry’s process, and a foundry will not put an unqualified material through its line: contamination control is the entire basis of the business. So a cannot simply be added to a shuttle design.

The routes that exist all work around that. Wafers or dies with the front end completed can be taken out and finished in a laboratory that is allowed to handle the material, which is essentially integration done by hand. A foundry can qualify a 2D deposition or itself, which is what the pilot lines at the large research institutes are working toward, and which is a multi-year commitment per material. Either way the question a shuttle asks is a useful discipline: what would it take for this layer to be acceptable in somebody else’s line?

For specialists

A shared fabrication run in which several customers’ designs are processed on the same wafers to split cost.

Where this comes from

MOSIS: IC prototyping and low volume production service Pina · International Conference on Microelectronic Systems Education, 4 (2001) cited by 24

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Layer transfer

Moving an atomically thin layer from where it was made to where it is needed – from the copper foil it grew on to a silicon wafer, or from a flake on tape onto another flake. The layer is too thin to pick up on its own, so it is carried on a polymer film or a soft stamp, put down, and the carrier removed. Each step risks tears, wrinkles, trapped bubbles and a film of leftover polymer, which is why transfer is often the dirtiest step in making a 2D device.

The step that moves a 2D layer from its growth substrate or exfoliation source to a target substrate or stack. Wet transfer coats the layer with a supporting polymer, usually PMMA, detaches it by etching the growth substrate or by electrochemical bubbling, and floats it onto the target before the polymer is dissolved. Dry transfer picks layers up with a viscoelastic PDMS stamp or a polymer film such as polycarbonate, often using the van der Waals adhesion of a top flake, and releases them by heating. The costs are cracks and wrinkles, trapped water, hydrocarbons and polymer residue, strain and doping, and – at wafer scale – yield that compounds with every transfer, which is why growth directly on the target and transfer-free routes are pursued.

Full explanation