FEOL and BEOL

Also called front end of line, back end of line

In plain words

The two halves of making a chip: the front end builds the in the silicon itself, and the back end adds the layers of metal wiring on top – at lower temperatures, so nothing underneath is damaged.

Going deeper

A chip is built in two stages: transistors first, in and on the silicon, then many levels of metal wiring above them. Everything in the second stage has to happen below roughly 400 °C, which is the central constraint on putting 2D materials into a real process.

Two halves of a process

The front end of line builds the transistors: wells, isolation, gate stacks, source and drain. Several of its steps are hot – dopant activation anneals reach about 1000 °C – which is fine, because nothing above them exists yet.

The back end of line then adds the interconnect: ten or more levels of copper wiring separated by low- and joined by vias, plus the contacts that reach down to the devices. By this point the transistors are finished and the wiring below is in place, so the collapses: processing must stay near or below 400 °C to avoid damaging dopant profiles, silicides and the dielectrics themselves. A middle of line is often named separately for the contacts between the two.

Why the split matters for 2D materials

Two-dimensional are attractive for back-end integration, because a layer under a nanometre thick can be added above existing circuits – the idea behind , where logic or memory is stacked on logic instead of placed beside it. Graphene and related materials have also been proposed for interconnect liners and as barriers.

The obstacle is temperature. Direct growth of a good film typically needs 700–900 °C, far above the back-end limit, so either growth must be brought down in temperature – metal–organic and plasma-assisted routes aim at this – or the layer must be grown elsewhere and , which is compatible with the budget but brings contamination, wrinkles and yield problems of its own.

What integration requires

A material is not integrable because one device works. It has to survive the rest of the flow: lithography and , dielectric deposition, chemical-mechanical polishing, and later thermal steps. It must be uniform over a 300 mm , not just on a ; contamination rules exclude many elements from a fab; and it has to be measurable with existing metrology so that yield can be controlled.

This is the gap between a laboratory record and a process option, and it is where most of the effort in industrial work now goes: wafer-scale growth, low-temperature transfer, contacts and dielectrics that behave the same across a wafer, and test structures with thousands of devices rather than one.

For specialists

Front end of line forms the transistors in the silicon; back end of line builds the metal interconnect layers above them at lower temperatures.

Where this comes from

High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity Kang et al. · Nature 520, 656 (2015) cited by 1,963
Graphene and two-dimensional materials for silicon technology Akinwande et al. · Nature 573, 507 (2019) cited by 1,738

Dielectric screening

The way a material weakens the pull between two charges inside it: its own electrons shift slightly and partly cancel the field between them. A sheet one atom thick has almost nothing around it to do this, so charges in it attract each other far more strongly than in a thick crystal – which is why light makes tightly bound pairs in 2D materials, and why whatever a sheet rests on changes its properties.

The reduction of the Coulomb interaction by the polarisation of bound electrons and ions and, in metals and doped layers, by free carriers, described by a dielectric function ε(q, ω). In a monolayer the field lines between distant charges run through the surroundings, so ε(q) approaches 1 as q → 0 and the screening is non-local and set by the environment. Exciton binding energies reach hundreds of meV, and a change of substrate or encapsulation shifts the quasiparticle gap by 100 meV or more while the optical gap barely moves.

Full explanation

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Layer transfer

Moving an atomically thin layer from where it was made to where it is needed – from the copper foil it grew on to a silicon wafer, or from a flake on tape onto another flake. The layer is too thin to pick up on its own, so it is carried on a polymer film or a soft stamp, put down, and the carrier removed. Each step risks tears, wrinkles, trapped bubbles and a film of leftover polymer, which is why transfer is often the dirtiest step in making a 2D device.

The step that moves a 2D layer from its growth substrate or exfoliation source to a target substrate or stack. Wet transfer coats the layer with a supporting polymer, usually PMMA, detaches it by etching the growth substrate or by electrochemical bubbling, and floats it onto the target before the polymer is dissolved. Dry transfer picks layers up with a viscoelastic PDMS stamp or a polymer film such as polycarbonate, often using the van der Waals adhesion of a top flake, and releases them by heating. The costs are cracks and wrinkles, trapped water, hydrocarbons and polymer residue, strain and doping, and – at wafer scale – yield that compounds with every transfer, which is why growth directly on the target and transfer-free routes are pursued.

Full explanation

Etching

Removing material on purpose, with a chemical or a plasma. In chip-making it carves patterns: a stencil of light-sensitive polymer protects some areas while a plasma eats away the rest. For 2D materials etching has three jobs: cutting flakes into shaped devices, thinning a crystal one layer at a time, and – for MXenes – making the material in the first place, by dissolving one kind of atom out of a layered ceramic so that the remaining sheets come apart.

Material removal by chemical reaction in a liquid (wet etching) or by reactive and physical processes in a plasma (dry etching, including reactive ion etching with oxygen-, fluorine- or chlorine-based chemistries, and atomic layer etching). For 2D materials it patterns channels and Hall bars through resist masks – oxygen plasma for graphene, fluorine-based plasmas for hBN and TMDCs – exposes edges in encapsulated stacks for edge contacts, thins crystals layer by layer, and selectively removes the A element, usually aluminium, from MAX phases with hydrofluoric acid or fluoride-containing acids to make MXenes. Its side effects are edge roughness and damage, residues, doping and plasma-induced defects in neighbouring layers, so the etched edge and its electronic states have to be considered in narrow devices.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation