The way almost every digital chip is built. Each logic gate pairs a that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.
Going deeper
Left: the simplest CMOS gate, an inverter, puts a p-type transistor above an n-type one, with the same input on both. Right: whatever the input, one of the two is off, so no current flows from supply to ground except in the moment of switching – which is why CMOS logic uses so little power standing still.
Two transistors that take turns
The simplest CMOS gate, the inverter, puts an transistor between its output and ground and a transistor between its output and the supply, with both gates wired to the input. A high input turns the n-type on and the p-type off, pulling the output to ground; a low input does the opposite. In either state one of the two transistors is off, so apart from the instant of switching no current flows from supply to ground, and a chip that is not switching draws only leakage.
Frank Wanlass and Chih-Tang Sah described the scheme in 1963, and over the following decades it displaced logic built from one kind of transistor because it wasted so much less power. Today it underlies processors, memories, microcontrollers and image , and “CMOS” has come to mean the whole silicon manufacturing process as well as the circuit style – which is why “CMOS-compatible” is the phrase a new material has to earn.
What CMOS asks of a new channel material
Both polarities. A circuit needs n-type and p-type transistors of similar strength, and for 2D that is harder than it sounds. Metal contacts on most pin the near the , so MoS2 conducts electrons readily and holes hardly at all. WSe2, with contacts of high- metals or heavily doped contact regions, is the leading p-type choice, and matching its drive current to that of the best n-type MoS2 devices remains an open problem.
Control and uniformity. Every transistor on a has to switch at nearly the same voltage, within tens of millivolts, and turn off by a large . As gates shrink the drain starts to pull on the channel and the transistor turns off less cleanly – the short-channel effects. A channel less than a nanometre thick keeps the gate in control of all of it, which is the main argument for 2D materials at the end of silicon scaling.
Getting onto a silicon chip
“CMOS-compatible” is a specific claim, not a compliment. It means materials the fab allows – gold, for instance, is kept out of front-end lines because it degrades silicon – temperatures the rest of the chip survives, wafers of 200 or 300 mm, and processes that a tool can repeat without a person placing . Two routes are being pursued. In the front end, 2D channels would replace silicon in future transistors, which industry roadmaps place in the 2030s. In the back end, 2D devices are built in the wiring layers above finished silicon circuits, which limits growth and transfer to about 400 °C.
The first demonstrations took the back-end route: graphene carrying light-absorbing has been built directly onto a CMOS image-sensor chip to make an infrared camera. For logic, the milestones to watch are functioning n- and p-type 2D transistors on the same wafer, wired into circuits with realistic supply voltages, and statistics over thousands of devices rather than a best one.
For specialists
Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe2 is the leading p-type candidate.