Monolithic 3D integration

In plain words

Building a second layer of electronic devices directly on top of a finished chip, instead of making two chips separately and joining them.

Going deeper

Monolithic 3D integration builds extra device layers directly on a finished circuit instead of bonding separate chips. The connections between layers can then be as fine as ordinary wiring rather than large through-silicon vias – provided everything added stays within the thermal budget of what lies beneath.

Stacking, two ways

The established way to get more devices into a given footprint is to make chips separately and bond them, connecting them with through-silicon vias. It works and is in production, but the vias are large – micrometres across – so the number of connections between layers is limited, and each die is thinned and aligned mechanically.

Monolithic integration instead builds the upper layers in place, on top of the completed lower ones. Alignment is lithographic rather than mechanical, and the vias between layers can be as small as ordinary . That allows orders of magnitude more connections between layers, which is what makes tightly coupled logic-on-memory arrangements conceivable.

Why 2D materials keep appearing in these proposals

Two properties fit. A channel under a nanometre thick adds almost nothing to the height of the stack, so many layers can be built without the structure becoming impractically tall. And 2D layers can be grown elsewhere and at low temperature, or grown at temperatures far below those needed for crystalline silicon on an amorphous surface – which is exactly the constraint that makes monolithic stacking difficult with conventional materials.

A demonstration that combined carbon-nanotube , resistive memory and silicon logic in one stacked chip made the case concretely: the upper layers were built at temperatures the lower ones could survive.

What has to work before it is real

The requirements are unforgiving. Every upper layer must be processed within the of everything beneath. Transfer or growth must be uniform across a 300 mm , not on one . Yield multiplies: two layers at 90% give 81%, and stacks are only worth building if each layer is nearly perfect. Heat has to escape through a structure that is now thicker and largely , and design tools have to handle the extra dimension.

The realistic near-term target is not logic on logic but memory or specialised layers on logic, where the upper layer can be slower and a modest density gain is still valuable – and where a failed upper layer does not ruin the chip beneath it.

For specialists

Building additional active device layers directly on top of a finished circuit rather than bonding separate chips.

Where this comes from

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip Shulaker et al. · Nature 547, 74 (2017) cited by 870

Layer transfer

Moving an atomically thin layer from where it was made to where it is needed – from the copper foil it grew on to a silicon wafer, or from a flake on tape onto another flake. The layer is too thin to pick up on its own, so it is carried on a polymer film or a soft stamp, put down, and the carrier removed. Each step risks tears, wrinkles, trapped bubbles and a film of leftover polymer, which is why transfer is often the dirtiest step in making a 2D device.

The step that moves a 2D layer from its growth substrate or exfoliation source to a target substrate or stack. Wet transfer coats the layer with a supporting polymer, usually PMMA, detaches it by etching the growth substrate or by electrochemical bubbling, and floats it onto the target before the polymer is dissolved. Dry transfer picks layers up with a viscoelastic PDMS stamp or a polymer film such as polycarbonate, often using the van der Waals adhesion of a top flake, and releases them by heating. The costs are cracks and wrinkles, trapped water, hydrocarbons and polymer residue, strain and doping, and – at wafer scale – yield that compounds with every transfer, which is why growth directly on the target and transfer-free routes are pursued.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Metal, semimetal and insulator

The three basic ways a solid treats electricity, set by how its electrons fill the energies open to them. In a metal they fill a band of energies only partly, so the smallest push sets them moving, and it conducts at any temperature. In an insulator they fill a band completely and a wide gap separates it from the next, so nothing can move. A semimetal sits in between: two bands just touch or overlap a little, leaving a small number of mobile electrons and holes. NbSe₂ is a metal, graphene a semimetal, hBN an insulator.

A classification by where the Fermi level falls in the band structure. In a metal it crosses a partly filled band, leaving a Fermi surface, a carrier density of order one per atom (about 10²² cm⁻³) and a resistivity that falls on cooling. In a band insulator it lies in a gap of several electronvolts; a semiconductor is an insulator whose gap is small enough to be doped or gated. A semimetal has a slight overlap between conduction and valence bands (graphite, bismuth, bulk WTe₂) or bands that touch at isolated points (graphene), giving low and nearly equal densities of electrons and holes. Interactions can open gaps that band theory does not predict: Mott insulators from half-filled bands, excitonic insulators from semimetals.

Full explanation