Silicon photonics

Also called integrated photonics

In plain words

Guiding light instead of electricity through tiny channels on a silicon chip, made with the same factories and tools as ordinary computer chips. Light carries data faster and with less loss over distance, so such chips already connect the servers in data centres. Silicon itself is poor at a few jobs – it hardly emits light, cannot detect the infrared light used in fibre networks, and switches light only weakly – and laid on top of the light channels are one way to add the missing functions.

Going deeper

A silicon strip on oxide traps light and guides it around a chip made in an ordinary chip factory. A 2D layer laid on top feels the light that leaks out of the strip: graphene, whose absorption a gate switches on and off, makes a compact modulator or detector, and other layers add emission, detection or non-volatile switching that silicon does poorly.

Light in a silicon wire

A silicon waveguide is a strip of silicon a few hundred nanometres wide on silicon dioxide. Because silicon bends light far more strongly than the oxide around it, light at the 1.3- and 1.55-micrometre wavelengths of fibre networks stays trapped in the strip and follows it round tight bends, so splitters, filters and switches fit on a chip a few millimetres across. The chips are made in the same factories as electronics, which is why silicon photonics has become the standard for optical links inside and between data centres.

Silicon’s weaknesses are well known: it emits light poorly, it is transparent – and therefore blind – at the telecom wavelengths, and its own ways of switching light are relatively weak or bulky. Germanium detectors and lasers bonded from other fill some of the gaps.

What a 2D layer adds

A layer laid on top of a waveguide feels the part of the light that leaks just outside the silicon, and over a few tens of micrometres that is enough. Graphene absorbs light over a very wide range of wavelengths, and a can switch that absorption off by emptying or filling its electron states: the result is a fast, compact modulator, first shown in 2011, and the same layer works as a fast detector. Thin MoTe₂, whose gap suits the near infrared in which silicon is transparent, emits and detects light on a waveguide, and the antimony sulfide and selenide switch the light in a waveguide and stay switched without power.

Because a 2D layer can be put on a finished waveguide at low temperature, it does not disturb the rest of the process – one reason graphene photonics is among the more advanced 2D technologies on the readiness scale.

What still stands in the way

The demonstrations work; the step to a foundry product is the hard part. Graphene has to be grown elsewhere and onto the photonic wafer without tears, residues or variations in , the contacts must have low resistance without adding optical loss, and every device across a 300-millimetre has to meet the same specifications as the silicon and germanium devices it would replace. Pilot lines that add 2D layers to standard photonic wafers are now testing exactly this.

For specialists

Photonic integrated circuits in silicon-on-, in which submicron silicon waveguides, with their high index contrast to the buried oxide, route light at telecom wavelengths through splitters, rings and gratings made with tools; germanium detectors and silicon carrier-depletion modulators are standard, and lasers are bonded or grown from III–V semiconductors. 2D materials couple to the evanescent field of the waveguide: graphene gives broadband, fast modulators and that can be integrated at wafer scale, thin MoTe₂ and black phosphorus emit and detect in the near infrared, and low-loss phase-change Sb₂S₃ and Sb₂Se₃ give non-volatile switches and tuning. The obstacles are wafer-scale transfer or growth, contacts, optical loss and reproducibility to foundry standards.

Where this comes from

The past, present, and future of silicon photonics Soref · IEEE Journal of Selected Topics in Quantum Electronics 12, 1678 (2006)
A graphene-based broadband optical modulator Liu et al. · Nature 474, 64 (2011)
A MoTe₂-based light-emitting diode and photodetector for silicon photonic integrated circuits Bie et al. · Nature Nanotechnology 12, 1124 (2017)
Graphene-based integrated photonics for next-generation datacom and telecom Romagnoli et al. · Nature Reviews Materials 3, 392 (2018) cited by 412
A new family of ultralow loss reversible phase-change materials for photonic integrated circuits: Sb₂S₃ and Sb₂Se₃ Delaney et al. · Advanced Functional Materials 30, 2002447 (2020) cited by 673

Gating

Changing a material by putting a voltage on a nearby electrode – a gate – separated from it by an insulator. The voltage pulls electrons into the material or pushes them out, as in every transistor. Because a 2D material is so thin, the gate reaches all of it, so the number of electrons can be dialled up and down continuously: a single device can be turned from insulator to metal, its magnetism strengthened, or superconductivity switched on. Two gates, above and below, can also apply an electric field across the layer.

Electrostatic control of carrier density and electric field through a gate coupled capacitively across a dielectric: the induced density equals the gate capacitance times the voltage beyond threshold, divided by the electron charge, reaching a few 10¹³ cm⁻² with oxide or hBN gates before breakdown. Dual gating sets density and perpendicular displacement field independently, opening the gap of bilayer graphene and tuning moiré flat bands. Ionic-liquid and solid-electrolyte gating form an electric double layer about a nanometre thick and reach 10¹⁴–10¹⁵ cm⁻², enough to induce superconductivity in MoS₂ or raise the Curie temperature of Fe₃GeTe₂, but can intercalate or react electrochemically and work only while the ions are mobile. Hysteresis from traps, contact effects and quantum capacitance are the usual caveats.

Full explanation

Layer transfer

Moving an atomically thin layer from where it was made to where it is needed – from the copper foil it grew on to a silicon wafer, or from a flake on tape onto another flake. The layer is too thin to pick up on its own, so it is carried on a polymer film or a soft stamp, put down, and the carrier removed. Each step risks tears, wrinkles, trapped bubbles and a film of leftover polymer, which is why transfer is often the dirtiest step in making a 2D device.

The step that moves a 2D layer from its growth substrate or exfoliation source to a target substrate or stack. Wet transfer coats the layer with a supporting polymer, usually PMMA, detaches it by etching the growth substrate or by electrochemical bubbling, and floats it onto the target before the polymer is dissolved. Dry transfer picks layers up with a viscoelastic PDMS stamp or a polymer film such as polycarbonate, often using the van der Waals adhesion of a top flake, and releases them by heating. The costs are cracks and wrinkles, trapped water, hydrocarbons and polymer residue, strain and doping, and – at wafer scale – yield that compounds with every transfer, which is why growth directly on the target and transfer-free routes are pursued.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Metal, semimetal and insulator

The three basic ways a solid treats electricity, set by how its electrons fill the energies open to them. In a metal they fill a band of energies only partly, so the smallest push sets them moving, and it conducts at any temperature. In an insulator they fill a band completely and a wide gap separates it from the next, so nothing can move. A semimetal sits in between: two bands just touch or overlap a little, leaving a small number of mobile electrons and holes. NbSe₂ is a metal, graphene a semimetal, hBN an insulator.

A classification by where the Fermi level falls in the band structure. In a metal it crosses a partly filled band, leaving a Fermi surface, a carrier density of order one per atom (about 10²² cm⁻³) and a resistivity that falls on cooling. In a band insulator it lies in a gap of several electronvolts; a semiconductor is an insulator whose gap is small enough to be doped or gated. A semimetal has a slight overlap between conduction and valence bands (graphite, bismuth, bulk WTe₂) or bands that touch at isolated points (graphene), giving low and nearly equal densities of electrons and holes. Interactions can open gaps that band theory does not predict: Mott insulators from half-filled bands, excitonic insulators from semimetals.

Full explanation

Complementary metal–oxide–semiconductor (CMOS)

The way almost every digital chip is built. Each logic gate pairs a transistor that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A 2D material becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.

Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, threshold voltages held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for back-end-of-line integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe₂ is the leading p-type candidate.

Full explanation