In plain words

How sharply a switches from off to on – the extra needed to raise the current tenfold. Ordinary transistors at room temperature cannot do better than about 60 millivolts.

Going deeper

Drain current on a logarithmic scale against gate voltage, with a line whose slope is 60 mV per decade and a steeper one beside it. how sharply it turns on drain current, per decade gate voltage 60 mV/dec steeper one decade of current for every 60 mV is as good as a normal transistor gets where the number comes from below threshold the carriers that make it over the barrier are the tail of a thermal distribution, so the current is exponential in the barrier height kT/q × ln 10 is 60 mV at room temperature interface traps make it worse by soaking up part of the gate's work how it has been beaten a ferroelectric in the gate stack can amplify the gate voltage: MoS₂ with hafnium zirconium oxide went below the thermal limit, hysteresis-free
Subthreshold swing is the gate voltage needed for a tenfold change in current. Thermal statistics put a floor of about 60 mV per decade on a conventional transistor at room temperature, and that floor is what sets how low a supply voltage can go.

Where 60 millivolts comes from

Below threshold, the current is carried by the carriers energetic enough to cross the channel barrier, and those are the tail of a thermal distribution. Raising the gate voltage lowers the barrier, and the population above it rises exponentially. Getting ten times the current therefore needs kT/q × ln 10 of barrier lowering, which is 60 mV at room temperature – the Boltzmann limit, or, less politely, the Boltzmann tyranny.

Real devices do worse, for a reason worth naming. The gate does not control the barrier one-for-one: part of its influence is absorbed by charging and discharging, and the swing is degraded by a factor that involves the ratio of the trap capacitance to the oxide capacitance. A measured swing above 60 mV/decade is therefore a direct statement about the gate stack, and it is one of the standard ways of arguing that an interface is bad.

Why it decides the power budget

The swing sets the exchange rate between off-current and supply voltage. A transistor has to be off enough that a chip of billions of them does not leak unacceptably, and on enough to switch quickly. The gate voltage between those two states is roughly the swing times the number of decades separating them, so a worse swing forces a higher supply voltage, and dynamic power grows as its square.

That is why the 60 mV floor is an obstacle rather than a detail: supply voltages have been stuck around 0.7 V for years, and the swing is the reason. It is also why a steep-slope device would matter even if it were mediocre in every other respect.

Beating it, and checking the claim

Two routes are pursued seriously. A tunnel FET replaces thermal emission with band-to-band tunnelling, whose current is not set by a thermal tail – at the cost of a low on-current. The other puts a in the gate stack so that, in the right regime, it amplifies the gate voltage seen by the channel. Combining that with a 2D channel has been demonstrated: a MoS2 transistor with a hafnium zirconium oxide layer in the gate stack reached a sub-thermionic swing while remaining essentially -free, with a maximum drain current of 510 µA/µm, and showed negative differential resistance at room temperature as a consequence of the negative capacitance.

The reason that description is so specific is that steep-slope claims are easy to fake accidentally. A hysteretic device sweeps steeply in one direction because charge is being trapped, not because the physics changed. A swing quoted from two points on a curve can be arbitrarily small. The claims worth believing are hysteresis-free, measured over several decades of current, reported in both sweep directions, and reproduced across devices.

For specialists

The gate voltage needed to change drain current tenfold below threshold; about 60 mV per decade is the room-temperature limit for conventional transistors.

Where this comes from

  1. Steep-slope hysteresis-free negative capacitance MoS2 transistors Si et al. · Nature Nanotechnology 13, 24 (2018) cited by 550