Thermal budget

In plain words

How much heat, and for how long, a chip can take at a given production step before the parts already built are damaged. New materials often have to be grown or added within that limit.

Going deeper

A thermal budget is not a single temperature but a temperature and a time together, because damage accumulates as atoms diffuse. Once transistors and wiring exist on a wafer, later steps have to stay cool – which is the central obstacle to adding 2D layers to a finished chip.

Temperature and time, not temperature alone

What damages a partly built is diffusion: dopants spreading out of their implanted profiles, metals reacting with silicon, hydrogen leaving passivated interfaces, changing structure. All of these follow rates that rise steeply with temperature, so the harm done depends on how hot and for how long.

That is why process engineers speak of a budget to be spent rather than a limit not to be crossed, and why rapid thermal processing exists: a few seconds at high temperature activate dopants while letting them spread far less than the long furnace anneals it replaced.

The numbers that matter for 2D materials

Front-end steps can be hot because nothing above them exists yet. Once the wiring is in place, the ceiling falls to roughly 400 °C. Transfers and lamination happen well below 200 °C; of gate oxides runs at 200–300 °C; contact anneals sit near the ceiling.

Direct growth of a good film usually needs 700–900 °C, which is far above that ceiling. Two routes exist: bring the growth temperature down, which is what metal–organic and plasma-assisted attempt, or grow elsewhere and transfer. Neither is solved. A demonstration of double-gated WS₂ built on 300 mm wafers inside a silicon fab showed that the flow can be made compatible in principle, which is what makes the question a process-engineering one rather than a physics one.

What it constrains besides growth

The budget shapes the whole device stack. Dielectrics must be deposited at low temperature and still be dense and pinhole-free; contacts must be annealed gently or not at all, which limits how far can be improved; and steps have to fit as well.

It also constrains repair. Many defects in 2D films can be healed by annealing in a atmosphere – at temperatures the rest of the wafer cannot take. This is a recurring pattern: the treatment that makes a material good on its own is often incompatible with the environment it has to live in, which is why laboratory-grade films and fab-compatible films are not the same thing.

For specialists

The maximum temperature–time exposure a process step may impose without damaging structures already on the wafer.

Where this comes from

High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity Kang et al. · Nature 520, 656 (2015) cited by 1,963
Wafer-scale integration of double gated WS₂-transistors in 300 mm Si CMOS fab Asselberghs et al. · IEEE International Electron Devices Meeting, 40.2.1 (2020) cited by 59

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Atomic layer deposition (ALD)

A way to coat a surface one layer of atoms at a time. Two chemicals take turns: the first sticks to every free spot on the surface but not to itself, the excess is pumped away, and the second reacts with what stuck, leaving one thin layer of, say, aluminium oxide. Repeating the pair builds the film with a precision of a fraction of a nanometre, even over deep, steep structures. It is how the gate insulators of modern computer chips are made – and on 2D materials it runs into a problem: their clean surfaces give the first chemical nothing to stick to.

Thin-film growth by alternating, self-limiting surface reactions of two precursors separated by purges – for Al₂O₃ trimethylaluminium and water, for HfO₂ a hafnium amide or chloride with water or ozone – typically at 100 to 300 °C, giving about 0.1 nm per cycle with sub-nanometre control and conformal coverage. It is the standard route to high-κ gate dielectrics in silicon CMOS. On the dangling-bond-free basal planes of graphene, TMDCs and hBN the first precursor finds no reactive sites, so nucleation starts only at steps, defects and residues, giving islands and pinholes. Seed layers (evaporated and oxidised Al, molecular layers), ozone or plasma functionalisation, low-temperature physisorption, or transferred and native-oxide dielectrics are used instead, each at a cost in thickness, interface traps or channel damage.

Full explanation

Passivation

Treating a surface so that it stops reacting with its surroundings and stops trapping electrons – by covering it with a thin protective layer, or by attaching atoms that tie up its loose bonds. Aluminium does it by itself: a skin of oxide a few nanometres thick is why aluminium window frames do not corrode away. A 2D material is all surface, so passivating it can decide whether it glows brightly, conducts well or survives in air at all.

The chemical or physical deactivation of a surface or interface: saturating dangling bonds and trap states (hydrogen on silicon, sulfur on III–V surfaces), compensating defects (superacid or thiol treatment of TMDC vacancies), or sealing with a dielectric such as Al₂O₃ or hBN. In 2D semiconductors it raises photoluminescence yield, lowers interface trap density and hysteresis, and slows oxidation; in perovskite solar cells a thin 2D perovskite layer passivates the surface of the 3D absorber.

Full explanation

Chalcogenide, halide and pnictide

Family names for compounds, taken from the element in them that carries the negative charge. Chalcogenides contain sulfur, selenium or tellurium; halides contain fluorine, chlorine, bromine or iodine; pnictides contain phosphorus, arsenic, antimony or bismuth. Most layered crystals belong to one of these families, and the catalogue groups many of them that way.

Compounds named for their most electronegative constituent: chalcogenides of group 16 (S, Se, Te; oxides are conventionally counted apart), halides of group 17 (F, Cl, Br, I) and pnictides of group 15 (P, As, Sb, Bi; nitrides usually keep their own name). Down each group the anion grows larger and less electronegative, so bonding turns more covalent, gaps shrink and spin–orbit coupling grows. Chalcogenides give the MX₂ semiconductors and metals, halides mostly ionic, often magnetic insulators built from edge-sharing octahedra, and pnictides many metals, semimetals and the parents of the iron-based superconductors; mixed-anion compounds such as oxychalcogenides and chalcohalides combine two.

Full explanation