Gate-all-around and CFET

Also called GAA

In plain words

Newer designs in which the controlling gate wraps completely around thin stacked channels – like gripping a hose with the whole hand rather than pinching it from one side. In the CFET version the two kinds of transistor a circuit needs are also stacked on top of each other to save space.

Going deeper

Each generation wraps the gate further around the channel, because a gate that surrounds the channel controls it better and lets the channel be shorter. The CFET takes the next step in the other direction: stacking the two device types on top of each other.

Why the gate keeps wrapping further round

A transistor turns off when the gate, not the drain, controls the channel potential. As channels shorten, the drain starts to compete, the device leaks, and the subthreshold slope degrades – effects. The fix has always been geometric: increase the fraction of the channel the gate surrounds, and shrink the channel’s thickness so no part of it is far from the gate.

Planar gave way to the FinFET, with the gate on three sides of a thin vertical fin. The , or gate-all-around, device closes the fourth side: the channel is a stack of horizontal sheets, each fully enclosed by the gate. That gives the best electrostatic control available for a given channel thickness, and the sheet width becomes a design knob, since drive current scales with it.

Stacking the complementary pair

The CFET attacks the other axis. A logic cell always needs both an and a device, and in every layout so far they sit side by side, which sets the cell’s width. Stacking one directly above the other – an n-type sheet over a p-type fin or sheet – removes that side-by-side requirement, and design-technology co-optimisation studies put the resulting area saving at about half for both standard cells and SRAM bit cells.

The cost is vertical complexity. Contacts and power now have to be reached through deep vias whose parasitic resistance dominates the device, so the gain depends on advances in contact metallisation with thin barriers. The process also has to control the elevation dimension – how high each layer sits – as carefully as it controls lithographic width, which is a different kind of manufacturing problem from the one the industry has spent decades solving.

Where a 2D channel would fit

This is the roadmap into which 2D are usually proposed. The sheets in a gate-all-around stack keep getting thinner, and thin silicon has a problem: below a few nanometres, falls sharply because carriers scatter from the sheet’s own surfaces and from thickness fluctuations. A semiconductor is thin by construction, with an atomically defined thickness and no on its surfaces, so in principle it does not pay that penalty.

What stands between the proposal and a device is everything the rest of this glossary is about: , the lack of a scalable on a surface with nothing to bond to, growth or transfer with acceptable uniformity, and variability measured over thousands of devices rather than a few. The architecture is not the obstacle – the integration is.

For specialists

Transistor architectures in which the gate surrounds stacked channel sheets; complementary FETs stack n- and p-type devices vertically.

Where this comes from

The complementary FET (CFET) for CMOS scaling beyond N3 Ryckaert et al. · IEEE Symposium on VLSI Technology, 141 (2018) cited by 254

Complementary metal–oxide–semiconductor (CMOS)

The way almost every digital chip is built. Each logic gate pairs a transistor that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A 2D material becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.

Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, threshold voltages held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for back-end-of-line integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe₂ is the leading p-type candidate.

Full explanation

Electron hole

Usually just called a hole: the empty place an electron leaves behind in an otherwise full band. It behaves like a particle of its own with a positive charge. When a neighbouring electron steps into the gap, the gap moves the other way – like the empty space in a queue of cars, which travels backwards as each car edges forward. Many materials conduct mainly with holes, and chips need both kinds of carrier.

An unoccupied state in an otherwise filled band, usually near the valence-band maximum, treated as a quasiparticle with positive charge and a positive effective mass set by the band curvature. Holes carry the current in p-type semiconductors and give a positive Hall coefficient. In 2D semiconductors good p-type transport is harder to obtain than n-type, largely because metal contacts pin the Fermi level nearer the conduction band.

Full explanation

Dangling bond

A bond left with nothing on the other end, on an atom at a surface that has lost the neighbour it was bonded to inside the crystal. Such bonds grab stray molecules and trap electrons, which is why ordinary surfaces are messy – and why layered crystals, whose sheets keep every bond inside themselves, split into faces that stay clean down to a single layer.

An unsaturated valence orbital at a surface, edge or defect where a covalent bond has been cut. In a bulk semiconductor such as silicon these states lie in the gap, trap charge and pin the Fermi level unless passivated by hydrogen or a grown oxide. The basal plane of a layered crystal has none, which is what allows van der Waals stacking without lattice matching and interfaces with few traps – and also why atomic layer deposition nucleates poorly on it. Edges, grain boundaries and vacancies do carry them, and are where 2D materials are chemically active.

Full explanation

Dielectric

An electrical insulator used for what it does in an electric field rather than for carrying current – the thin layer inside a capacitor, or the insulator that separates a transistor’s gate from its channel. A good dielectric blocks current completely, withstands a strong field without breaking down and, for gates, has a high permittivity, so that a voltage on the gate pulls many charges into the channel. For 2D transistors the dielectric is as hard to get right as the 2D layer itself.

An insulator characterised by its permittivity κ, band gap and band offsets to the channel, breakdown field, leakage, and density of fixed charge and traps at the interface and in the bulk (border traps). Silicon technology moved from SiO₂ (κ ≈ 3.9) to hafnium-based high-κ oxides (κ ≈ 20–25) to keep gate control at sub-nanometre equivalent oxide thickness. For 2D channels, hBN gives clean, trap-poor interfaces but a low κ of about 3–4 and is hard to grow at wafer scale; ALD oxides nucleate poorly on basal planes; alternatives include crystalline CaF₂, native oxides such as Bi₂SeO₅ on Bi₂O₂Se, and molecular crystals. Reliability – hysteresis, bias-temperature instability and time-dependent breakdown – is the yardstick for any dielectric meant for products.

Full explanation

Wafer and wafer-scale growth

A wafer is the thin, round slice of ultra-pure silicon – today 300 millimetres across – on which computer chips are made, hundreds at a time. Wafer-scale growth means making a 2D material evenly over a whole wafer rather than as scattered flakes, which is what any factory needs. For the best 2D materials that is still hard: a sheet one atom thick has to have the same thickness, quality and orientation from one edge of a dinner-plate-sized disc to the other.

The substrate format of the semiconductor industry – 200 and 300 mm silicon wafers, with sapphire, SiC and glass for particular processes – and the scale at which a material must be grown, transferred and processed to enter manufacturing. Wafer-scale growth of 2D materials uses CVD and MOCVD of TMDCs, CVD of graphene and hBN, and MBE, with targets of uniform layer number, low defect and grain-boundary density and, increasingly, a single orientation on vicinal sapphire or Cu(111). The obstacles are the growth temperature against the thermal budget of a finished wafer (growth on the back end of line needs to stay below about 400 to 450 °C), the transfer from growth substrate to device wafer, and metrology that confirms thickness and quality across the wafer at production speed.

Full explanation