On/off ratio

In plain words

How much more current a lets through when it is switched on than when it is switched off. A switch for digital logic needs at least ten thousand, and far more in chips that spend most of their time idle; graphene, which has no , manages only about ten, which is why it cannot replace silicon in logic.

Going deeper

Left: a transistor with a band gap, here monolayer MoS₂, can turn its current down by about eight factors of ten; gapless graphene manages about one. Right: below threshold the current falls at best tenfold per 60 mV at room temperature, and the gap caps how far it can fall before carriers of the other sign take over; logic needs at least 10⁴, low-power chips 10⁶ or more.

Why a switch needs a large ratio

A logic chip holds billions of transistors, and at any moment nearly all of them are off. Their combined leakage sets the power drawn while nothing is happening, while the on current sets how fast each transistor can charge the next one. A chip therefore needs both a large on current and a tiny off current, and the ratio between them is the first test of any new channel material: at least 10⁴ for logic, and 10⁶ or more for low-power chips that spend most of their time idle.

Other uses ask for less. A radio-frequency amplifier works around a single operating point and never has to switch fully off, so a small ratio does it no harm – which is why graphene transistors were first taken seriously for high-frequency analogue circuits rather than logic.

What sets it

Below threshold the current is carried by the few electrons with enough thermal energy to cross the barrier the gate controls, and at room temperature that population changes at most tenfold for every 60 mV the barrier moves. The ratio therefore grows with the voltage window available and with how close the comes to that limit. It is also capped by the band gap: push the barrier further and carriers of the other sign start to flow through the channel, so a small gap limits the ratio however good the gate. Graphene, with no gap at all, manages about 2 to 20 at room temperature.

MoS₂, with a gap of nearly 2 eV, reached a ratio of about 10⁸ in the first single-layer transistors in 2011. bring leakage of their own – the drain lowers the barrier, and carriers tunnel from source to drain beneath it – and here a channel less than a nanometre thick helps, because the gate keeps control of all of it.

Reading a reported ratio

A ratio on its own can mislead in four ways. The voltage window: a ratio taken across a 60 V sweep of a on thick oxide says little about a transistor that has to switch within a volt. The off current: many very large ratios are really the noise floor of the instrument, a picoampere or so, so the off current should be given in amperes per micrometre of width, next to that floor. The conditions: drain voltage, temperature, and whether the value comes from one champion device or a distribution. And the on current: a huge ratio with a tiny on current still makes a poor switch.

For these reasons transistor benchmarks fix the off current and the supply voltage – for example 100 nA/µm at about 0.7 V – and compare the on current reached there, which folds the ratio, the swing and the into one number that can be set beside silicon’s.

For specialists

The ratio of the drain current with the transistor switched on to the current with it switched off, at a stated supply voltage. Below threshold the current falls at best tenfold per 60 mV of gate voltage at room temperature, so a ratio of 10⁶ needs at least 0.36 V of swing, and the off current is floored by leakage over the gap, band-to-band and source-to-drain tunnelling, and gate leakage. Monolayer MoS₂ transistors reached about 10⁸; gapless graphene stays near 10 at room temperature. Benchmarks compare the on current at a fixed off current and supply voltage rather than the ratio alone.

Where this comes from

Single-layer MoS₂ transistors Radisavljevic et al. · Nature Nanotechnology 6, 147 (2011) cited by 14,996
Graphene transistors Schwierz · Nature Nanotechnology 5, 487 (2010) cited by 5,270

Complementary metal–oxide–semiconductor (CMOS)

The way almost every digital chip is built. Each logic gate pairs a transistor that conducts with electrons with one that conducts with holes, so one of the two is always off and the gate draws almost no current except while it switches. A 2D material becomes useful for logic only if both kinds of transistor can be made from it, or if it can be added to a silicon chip without harming it.

Logic in which n- and p-channel field-effect transistors are wired in series between supply and ground, so that in either stable state one of them is off and static power is set by leakage alone. It demands n- and p-type devices of comparable drive, threshold voltages held within tens of millivolts across a wafer, and a process compatible with the silicon line – about 400 °C at most for back-end-of-line integration. For 2D channels the p-type half is the harder one: most TMDCs conduct n-type with common contact metals, and WSe₂ is the leading p-type candidate.

Full explanation

Gating

Changing a material by putting a voltage on a nearby electrode – a gate – separated from it by an insulator. The voltage pulls electrons into the material or pushes them out, as in every transistor. Because a 2D material is so thin, the gate reaches all of it, so the number of electrons can be dialled up and down continuously: a single device can be turned from insulator to metal, its magnetism strengthened, or superconductivity switched on. Two gates, above and below, can also apply an electric field across the layer.

Electrostatic control of carrier density and electric field through a gate coupled capacitively across a dielectric: the induced density equals the gate capacitance times the voltage beyond threshold, divided by the electron charge, reaching a few 10¹³ cm⁻² with oxide or hBN gates before breakdown. Dual gating sets density and perpendicular displacement field independently, opening the gap of bilayer graphene and tuning moiré flat bands. Ionic-liquid and solid-electrolyte gating form an electric double layer about a nanometre thick and reach 10¹⁴–10¹⁵ cm⁻², enough to induce superconductivity in MoS₂ or raise the Curie temperature of Fe₃GeTe₂, but can intercalate or react electrochemically and work only while the ions are mobile. Hysteresis from traps, contact effects and quantum capacitance are the usual caveats.

Full explanation